MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 148

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.12
Read: Anytime
Write: anytime
4.3.2.13
Read: Anytime
Write: Anytime
148
IEN[15:8]
Reset
Reset
IEN[7:0]
Field
Field
7:0
7:0
W
W
R
R
IEN15
IEN7
ATD Input Enable Register 0 (ATDDIEN0)
ATD Input Enable Register 1 (ATDDIEN1)
0
0
7
7
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
IEN14
IEN6
0
0
6
6
Figure 4-14. ATD Input Enable Register 0 (ATDDIEN0)
Figure 4-15. ATD Input Enable Register 1 (ATDDIEN1)
Table 4-23. ATDDIEN0 Field Descriptions
Table 4-24. ATDDIEN1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
IEN13
IEN5
0
0
5
5
IEN12
IEN4
0
0
4
4
Description
Description
IEN11
IEN3
0
0
3
3
IEN10
IEN2
0
0
2
2
Freescale Semiconductor
IEN9
IEN1
0
0
1
1
IEN8
IEN0
0
0
0
0