MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 695

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.3
A summary of the registers associated with the DBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
19.3.1
This section consists of the DBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG and COMRV[1:0]
Freescale Semiconductor
1. This represents the contents if the comparator A or C control register is blended into this address
2. This represents the contents if the comparator B or D control register is blended into this address
Address
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
0x0028
Memory Map and Register Definition
(COMPB/D)
DBGXCTL
(COMPA/C)
DBGXCTL
DBGSCRX
DBGTCR
DBGTBH
DBGCNT
Register
DBGTBL
DBGSR
Register Descriptions
DBGC1
DBGC2
Name
1
2
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
Bit 15
Bit 7
ARM
TBF
Bit 7
SZE
0
0
0
0
TSOURCE
Figure 19-2. DBG Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
= Unimplemented or Reserved
EXTF
TRIG
NDB
SZ
14
6
0
0
6
0
XGSBPE
TAG
TAG
13
5
0
0
5
0
TRANGE
BDM
BRK
BRK
12
4
0
0
4
0
CNT
SC3
Chapter 19 S12X Debug (S12XDBGV2) Module
RW
RW
11
3
0
3
TRCMOD
DBGBRK
CDCM
Figure
SSF2
RWE
RWE
SC2
10
2
2
19-2. Detailed
SSF1
SRC
SRC
SC1
1
9
1
COMRV
TALIGN
ABCM
COMPE
COMPE
SSF0
Bit 0
Bit 8
Bit 0
SC0
697