MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 136

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
136
FRZ[1:0]
Field
FIFO
1:0
2
Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the
result registers based on the conversion sequence; the result of the first conversion appears in the first result
register, the second result in the second result register, and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the
conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to
ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is
continuos conversion (SCAN=1) or triggered conversion (ETRIG=1).
Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear
mode may or may not be useful in a particular application to track valid data.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze
period.
S8C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 4-8. ATDCTL3 Field Descriptions (continued)
Table 4-9. Conversion Sequence Length Coding
S4C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MC9S12XDP512 Data Sheet, Rev. 2.21
Table
S2C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4-10. Leakage onto the storage node and comparator reference capacitors
S1C
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Number of Conversions
per Sequence
16
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
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