MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 760

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.7.4
Read: Anytime
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further triggers on the same channel have no affect.
20.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
762
Address: 0x0027
0x002A
0x002B
0x002C
0x002D
0x002E
0x0028
0x0029
0x002F
Reset
W
R
Comparator Register Descriptions
0
0
7
Debug Match Flag Register (DBGMFR)
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
= Unimplemented or Reserved
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
0
0
6
Figure 20-12. Debug Match Flag Register (DBGMFR)
CONTROL
Table 20-26. Comparator Register Layout
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
0
0
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
MC3
0
3
MC2
0
2
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparator A and C only
Freescale Semiconductor
MC1
—
—
—
—
0
1
MC0
0
0