MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 384

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
8.4.2
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period
register and a duty register (each are 8-bit). The waveform output period is controlled by a match between
the period register and the value in the counter. The duty is controlled by a match between the duty register
and the counter value and causes the state of the output to change during the period. The starting polarity
of the output is also selectable on a per channel basis. Shown below in
for the PWM timer.
8.4.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual
PWM waveform is not available on the associated PWM output until its clock source begins its next cycle
due to the synchronization of PWMEx and the clock source. An exception to this is when channels are
concatenated. Refer to
384
Clock Source
PWMEx
(Clock Edge
PWM Channel Timers
PWM Enable
Sync)
Gate
The first PWM cycle after enabling the channel can be irregular.
Up/Down
Section 8.4.2.7, “PWM 16-Bit Functions”
8-Bit Counter
Figure 8-19. PWM Timer Channel Block Diagram
PWMCNTx
Q
Q
Reset
T
R
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
8-bit Compare =
8-bit Compare =
PWMDTYx
PWMPERx
CAEx
for more detail.
Figure 8-19
T
R
Q
Q
PPOLx
From Port PWMP
M
Data Register
U
X
is the block diagram
Freescale Semiconductor
M
U
X
To Pin
Driver