ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 123

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)
MSR Address
Type
Reset Value
IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF Tag and Target RAMs, and to get an indication of
whether the BIST run passed or failed. There are separate BIST controllers for the Tag RAM and for the Target RAMs. A
MSR read of IF_BIST_MSR causes BIST to be run.
IF_BIST_MSR can only be run when the level-1 COF cache, the level-0 COF cache, and the return stack is disabled in the
IF_CONFIG MSR. If the COF cache is enabled, reading IF_BIST_MSR does not cause BIST to be run, and returns zero.
After BIST has been run by reading IF_BIST_MSR, the contents of the IF Tag RAMs is invalidated (cleared).
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:2
Bit
1
0
Name
RSVD
TGT_PASS
TAG_PASS
00001140h
RO
00000000_00000000h
Description
Reserved.
Target RAM BIST Status.
0: Target RAM BIST did not pass. (Default)
1: Target RAM BIST passed.
Tag RAM BIST Status.
0: Tag RAM BIST did not pass. (Default)
1: Tar RAM BIST passed.
IF_BIST_MSR Bit Descriptions
IF_BIST_MSR Register Map
RSVD
RSVD
9
8
33234H
7
6
5
4
3
2
1
123
0