ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 516
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ALXD800EEXJCVD C3
Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJCVD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJCVD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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6.12.1.3 GLD SMI MSR (GLD_MSR_SMI)
MSR Address
Type
Reset Value
6.12.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address
Type
Reset Value
516
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:35
34:32
31:3
Bit
2:0
Name
RSVD
SMI_STATUS
RSVD
SMI_MASK
58002002h
R/W
00000000_00000007h
58002003h
R/W
00000000_00000019h
33234H
Description
Reserved.
SMI Status. There are three SMI status sources. For each source, the individual bit has
the following meaning:
0: SMI not pending.
1: SMI pending.
Writing a 1 to the bit clears the status.
Bit 34: EEPROM Operation Complete SMI.
Bit 33: AES Context B Complete SMI.
Bit 32: AES Context A Complete SMI.
Reserved.
SMI Masks. There are three SMI status masks. For each source, the individual bit has
the following meaning:
0: Enable. Unmask the SMI.
1: Disable. Mask the SMI.
Bit 2: When enabled (0), allows EEPROM Operation Complete SMI.
Bit 1: When enabled (0), allows AES Context B Complete SMI.
Bit 0: When enabled (0), allows AES Context A Complete SMI.
GLD_MSR_SMI Bit Descriptions
GLD_MSR_SMI Register Map
RSVD
RSVD
AMD Geode™ LX Processors Data Book
9
Security Block Register Descriptions
8
7
6
5
4
3
SMI_MASK
SMI_STAT
2
US
1
0
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