ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 551

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14.2.9 GLCP Clock Control (GLCP_CLKOFF)
MSR Address
Type
Reset Value
This register has bits that, when set, force clocks off using GeodeLink™ Clock Control (GLCC) logic in the system. This is
for debugging only, and should not be used for power management.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:34
Bit
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
Name
RSVD
VIPVIP
VIPGLIU
AES
AESGLIU
AESEE
GLCPDBG
GLCPGLIU
GLCPPCI
VPVOP
VPDOT_2
VPDOT_1
VPDOT_0
VPGLIU_1
VPGLIU_0
PCIPCIF
PCIPCI
PCIGLIU
GLIU1_1
GLIU1_0
DCGLIU_1
DCGLIU_0
RSVD
4C000010h
R/W
00000000_00000000h
Description
Reserved.
VIP VIPCLK Off. When set, disables VIP VIPCLK.
VIP GLIU Clock Off. When set, disables VIP GLIU clock.
AES Core Functional Clock Off. When set, disables AES encryption/decryption
clock.
AES GLIU Clock Off. When set, disables AES GLIU interface clock.
AES EEPROM Clock Off. When set, disables AES EEPROM clock.
GLCP Debug Clock Off. When set, disables GLCP DBG logic clock.
GLCP GLIU Clock Off. When set, disables GLCP GLIU clock.
GLCP GIO PCI Clock Off. When set, disables GLCP’s GIO PCI clock.
VP VOP Clock Off. When set, disables VOP logic clock.
VP DOT Clock 2 Off. When set, disables VP Dot Clock 2 (vp_vid).
VP Dot Clock 1 Off. When set, disables VP Dot Clock 1 (lcd_pix).
VP Dot Clock 0 Off. When set, disables VP Dot Clock 0 (vp_pix).
VP GLIU Clock 1 Off. When set, disables VP GLIU Clock 1 (lcd).
VP GLIU Clock 0 Off. When set, disables VP GLIU Clock 0 (vp).
Fast PCI Clock Off. When set, disables fast PCI clock inside GLPCI block.
PCI Clock Off. When set, disables normal PCI clock inside GLPCI block.
GLPCI Clock Off. When set, disables clock entering GLPCI block.
GLIU1 Clock Off. When set, disables main clock to secondary GLIU.
GLIU1 Timer Logic Clock Off. When set, disables clock to timer logic of secondary
GLIU.
DC GLIU Clock 1 Off. When set, disables DC GLIU Clock 1 (VGA).
DC GLIU Clock 0 Off. When set, disables DC GLIU Clock 0 (DC).
Reserved. Unused bit, reads what was written, value written has no effect.
GLCP_CLKOFF Bit Descriptions
GLCP_CLKOFF Register Map
RSVD
9
8
33234H
7
6
5
4
3
2
1
551
0