ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 487

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Input Port Register Descriptions
6.10.1.5 GLD Power Management Register (GLD_MSR_PM)
MSR Address
Type
Reset Value
6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
MSR Address
Type
Reset Value
This register is reserved for internal use by AMD and should not be written to.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:4
Bit
3
2
1
0
Name
RSVD
RSVD
P1
RSVD
P0
54002004h
R/W
000000000_ 00000005h
54002005h
R/W
000000000_ 00000000h
Description
Reserved.
Reserved. Always set to 0.
VIP Clock Power Mode.
0: Disable clock gating. VIP clock is always ON.
1: Enable active hardware clock gating.
The VIP input clock to the video input block is enabled when this bit is 0. When this bit is
1, the VIP input clock is enabled whenever the VIP reset bit (VIP Memory Offset 00h[0])
is 0 or if VIP_MODE (VIP Memory Offset 00h bit [3:1]) is in a non 000 state. This bit
defaults to 1.
Reserved. Always set to 0.
GLIU Clock Power Mode.
0: Disable clock gating. GLIU clock is always ON.
1: Enable active hardware clock gating.
GLIU clock is always on if the VIP reset bit (VIP Memory Offset 00h[0]) is 0. When the
VIP reset bit is 1 and this bit is 1, the internal VIP GLIU clocks are only turned on in
response to requests (memory mapped read/writes and MSR read/writes) from the GLIU.
This bit defaults to 1.
GLD_MSR_PM Bit Descriptions
GLD_MSR_PM Register Map
RSVD
RSVD
9
8
33234H
7
6
5
4
3
0 P1 0 P0
2
1
487
0