ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 384
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ALXD800EEXJCVD C3
Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJCVD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJCVD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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6.6.22.4 Video DAC Palette Mask
Read Address
Write Address
Type
Reset Value
6.6.23
The Extended registers are accessed by writing an index value to the CRTC Index register (3B4h or 3D4h) and reading or
writing the register using the CRTC Data register (3B5h or 3D5h). See the description of the I/O Address Select bit in the
Section 6.6.17.1 "VGA Miscellaneous Output" on page 356 for more information on the I/O address of the CRTC registers.
Note 1. R/W when unlocked, RO otherwise (see Section 6.6.23.1 "ExtendedRegisterLock" for details).
384
Bit
7:0
0030h
Index
043h
044h
047h
048h
060h
061h
070h
071h
VGA Block Extended Registers
Name
PAL_MSK
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
3C6h
3C6h
R/W
00h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
33234H
Register
ExtendedRegisterLock
ExtendedModeControl
ExtendedStartAddress
WriteMemoryAperture
ReadMemoryAperture
BlinkCounterCtl (for Sim/Test)
BlinkCounter (for Sim/Test)
VGALatchSavRes
DACIFSavRes
Video DAC Palette Mask Register Bit Descriptions
Description
Palette Mask. These bits enable their respective color bits between the final VGA 8-bit
pixel output and the DAC palette. The bits are ANDed with the incoming VGA pixel value
and the result used to address the palette RAM.
Table 6-59. Extended Registers Summary
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
Reset Value
FFh
00h
00h
00h
00h
00h
00h
00h
00h
Reference
Page 385
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Page 387
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