ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 508

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT)
VIP Memory Offset 78h
Type
Reset Value
6.10.2.30 VIP Task A U Even Offset (VIP_TASK_A_U_EVEN_OFFSET)
VIP Memory Offset 7Ch
Type
Reset Value
508
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:24
23:0
31:0
Bit
Bit
VERTICAL_WINDOW
Name
VERTICAL_
WINDOW
VERTICAL_
COUNT
Name
TASK_A_U_
EVEN_OFFSET
R/W
00000000h
R/W
00000000h
33234H
VIP_TASK_A_U_EVEN_OFFSET Bit Descriptions
Description
Vertical Window. This field defines the number of VIP clocks the input VBLANK can
vary before it is considered invalid. (16-4095 clocks)
Vertical Count. This field provides the check point for verifying that the input data stream
is maintaining consistent VSYNC timing. This count is the minimum number of VIP clocks
expected in an input field (interlaced video) or frame (non-interlaced video). If the number
of video clocks between rising edges of VBLANK is less then this number (or greater
then VERTICAL_COUNT + VERTICAL_WINDOW), a VSYNC error interrupt is gener-
ated and the video_ok output signal is forced low indicating invalid input video. (0-
16,777,215 clocks)
Note:
Description
Task A U Even Offset. This register determines the starting address of the U buffer for
the even field when in interlaced input mode and data is stored in planar format. This reg-
ister is not used when in non-interlaced input mode. The value in this register needs to be
32-byte aligned. (Bits [4:0] are required to be 00000.)
VIP_TASK_A_U_EVEN_OFFSET Register Map
VIP_SYNC_ERR_COUNT Bit Descriptions
VIP_SYNC_ERR_COUNT Register Map
TASK_A_U_EVEN_OFFSET
A 60 Hz VBLANK rate @75 MHz input clock = 1,250,000 clocks.
VERTICAL_COUNT
AMD Geode™ LX Processors Data Book
9
9
Video Input Port Register Descriptions
8
8
7
7
6
6
5
5
4
4
Program to 00000
3
3
2
2
1
1
0
0