PIC10F322T-I/OT Microchip Technology, PIC10F322T-I/OT Datasheet - Page 162
PIC10F322T-I/OT
Manufacturer Part Number
PIC10F322T-I/OT
Description
896 B Flash, 64 B RAM, 4 I/O, 8bit ADC, PWM, CLC, DDS, CWG, TEMP Indicator, 2.3V
Manufacturer
Microchip Technology
Datasheet
1.PIC10F320-IOT.pdf
(210 pages)
Specifications of PIC10F322T-I/OT
Core
RISC
Processor Series
PIC10F
Data Bus Width
8 bit
Maximum Clock Frequency
31 KHz
Program Memory Size
512 B
Data Ram Size
64 B
Number Of Programmable I/os
4
Number Of Timers
2
Operating Temperature Range
- 40 C to + 85 C
Package / Case
SOT-23-6
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 85 C
Program Memory Type
Flash
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC10F322T-I/OT
Manufacturer:
VISHAY
Quantity:
11 490
Part Number:
PIC10F322T-I/OT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC10(L)F320/322
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41585A-page 162
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 f 127
0 b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction.
Call Subroutine
[ label ] CALL k
0 k 2047
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
None
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
Clear W
[ label ] CLRW
None
00h (W)
1 Z
Z
W register is cleared. Zero bit (Z)
is set.
Clear f
[ label ] CLRF
0 f 127
00h (f)
1 Z
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
f
Preliminary
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DECF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Complement f
(f) (destination)
Z
TO, PD
[ label ] COMF
0 f 127
d [0,1]
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Decrement f
[ label ] DECF f,d
0 f 127
d [0,1]
(f) - 1 (destination)
Z
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
2011 Microchip Technology Inc.
f,d
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