PIC10F322T-I/OT Microchip Technology, PIC10F322T-I/OT Datasheet - Page 48

• Manufacturer Part Number: PIC10F322T-I/OT
• Description: 896 B Flash, 64 B RAM, 4 I/O, 8bit ADC, PWM, CLC, DDS, CWG, TEMP Indicator, 2.3V
• Manufacturer: Microchip Technology

Specifications of PIC10F322T-I/OT

• Core: RISC
• Processor Series: PIC10F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 31 KHz
• Program Memory Size: 512 B
• Data Ram Size: 64 B
• Number Of Programmable I/os: 4
• Number Of Timers: 2
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOT-23-6
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

PIC10(L)F320/322
6.6.3
The PIR1 register contains the interrupt flag bits, as
shown in
REGISTER 6-3:
DS41585A-page 48
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Register
PIR1 REGISTER
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion completed
0 = The A/D conversion is not complete
Unimplemented: Read as ‘0’
NCO1IF: Numerically Controlled Oscillator Interrupt Flag bit
1 = NCO1 overflow occurred (must be cleared in software)
0 = No NCO1 overflow
CLC1IF: Configurable Logic Block Rising Edge Interrupt Flag bit
1 = CLC interrupt occurred (must be cleared in software)
0 = No CLC Interrupt
Unimplemented: Read as ‘0’
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match
Note: The match must occur the number of times specified by the TMR2 postscaler
Unimplemented: Read as ‘0’
6-3.
R/W-0/0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
R/W-0/0
NCO1IF
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
CLC1IF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
—
 2011 Microchip Technology Inc.
R/W-0/0
TMR2IF
(Register
U-0
—
17-1).
bit 0