PIC10F322T-I/OT Microchip Technology, PIC10F322T-I/OT Datasheet - Page 51

• Manufacturer Part Number: PIC10F322T-I/OT
• Description: 896 B Flash, 64 B RAM, 4 I/O, 8bit ADC, PWM, CLC, DDS, CWG, TEMP Indicator, 2.3V
• Manufacturer: Microchip Technology

Specifications of PIC10F322T-I/OT

• Core: RISC
• Processor Series: PIC10F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 31 KHz
• Program Memory Size: 512 B
• Data Ram Size: 64 B
• Number Of Programmable I/os: 4
• Number Of Timers: 2
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOT-23-6
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

7.0
The Power-down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions
exist:
1.
2.
3.
4.
5.
6.
7.
8.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following condi-
tions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• CWG and NCO modules using HFINTOSC
I/O pins that are high-impedance inputs should be
pulled to V
rents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See
“Fixed Voltage Reference (FVR)”
tion on these modules.
 2011 Microchip Technology Inc.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
CPU clock is disabled.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
ADC is unaffected, if the dedicated FRC clock is
selected.
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high-
impedance).
Resets other than WDT are not affected by
Sleep mode.
POWER-DOWN MODE (SLEEP)
DD
or V
SS
externally to avoid switching cur-
for more informa-
Section 12.0
Preliminary
7.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
4.
5.
6.
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to
“Determining the Cause of a
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
The Complementary Waveform Generator (CWG) and
the Numerically Controlled Oscillator (NCO) modules
can utilize the HFINTOSC oscillator as their respective
clock source. Under certain conditions, when the HFIN-
TOSC is selected for use with the CWG or NCO mod-
ules, the HFINTOSC will remain active during Sleep.
This will have a direct effect on the Sleep mode current.
Please refer to
Generator (CWG) Module”
Controlled Oscillator (NCO) Module”
mation.
External Reset input on MCLR pin, if enabled
BOR Reset, if enabled
POR Reset
Watchdog Timer, if enabled
Any external interrupt
Interrupts by peripherals capable of running dur-
ing Sleep (see individual peripheral for more
information)
PIC10(L)F320/322
Wake-up from Sleep
21.0 “Complementary Waveform
and
Reset”.
20.0 “Numerically
DS41585A-page 51
for more infor-
Section 5.9