PIC10F322T-I/OT Microchip Technology, PIC10F322T-I/OT Datasheet - Page 54

• Manufacturer Part Number: PIC10F322T-I/OT
• Description: 896 B Flash, 64 B RAM, 4 I/O, 8bit ADC, PWM, CLC, DDS, CWG, TEMP Indicator, 2.3V
• Manufacturer: Microchip Technology

Specifications of PIC10F322T-I/OT

• Core: RISC
• Processor Series: PIC10F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 31 KHz
• Program Memory Size: 512 B
• Data Ram Size: 64 B
• Number Of Programmable I/os: 4
• Number Of Timers: 2
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOT-23-6
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

PIC10(L)F320/322
8.1
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 24.0 “Electrical Specifications”
LFINTOSC tolerances.
8.2
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word. See
8.2.1
When the WDTE bits of Configuration Word are set to
‘11’, the WDT is always on.
WDT protection is active during Sleep.
8.2.2
When the WDTE bits of Configuration Word are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
8.2.3
When the WDTE bits of Configuration Word are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See
for more details.
TABLE 8-1:
TABLE 8-2:
DS41585A-page 54
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Exit Sleep
Change INTOSC divider (IRCF bits)
WDTE<1:0>
Independent Clock Source
WDT Operating Modes
11
10
01
00
Table
WDT IS ALWAYS ON
WDT IS OFF IN SLEEP
WDT CONTROLLED BY SOFTWARE
8-1.
WDT OPERATING MODES
WDT CLEARING CONDITIONS
SWDTEN
X
X
1
0
X
Conditions
Device
Awake
Mode
Sleep
X
X
X
Disabled
Disabled
Disabled
Table 8-1
Active
Active
Active
Mode
for the
WDT
Preliminary
8.3
The WDTPS bits of the WDTCON register set the time-
out period from 1 ms to 256 seconds (nominal). After a
Reset, the default time-out period is 2 seconds.
8.4
The WDT is cleared when any of the following condi-
tions occur:
• Any Reset
• CLRWDT instruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail
• WDT is disabled
See
8.5
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See
Register 2-1
Table 8-2
Time-Out Period
Clearing the WDT
Operation During Sleep
Section 2.0 “Memory Organization”
for more information.
for more information.
 2011 Microchip Technology Inc.
Unaffected
Cleared
WDT
and