PIC10F322T-I/OT Microchip Technology, PIC10F322T-I/OT Datasheet - Page 45

• Manufacturer Part Number: PIC10F322T-I/OT
• Description: 896 B Flash, 64 B RAM, 4 I/O, 8bit ADC, PWM, CLC, DDS, CWG, TEMP Indicator, 2.3V
• Manufacturer: Microchip Technology

Specifications of PIC10F322T-I/OT

• Core: RISC
• Processor Series: PIC10F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 31 KHz
• Program Memory Size: 512 B
• Data Ram Size: 64 B
• Number Of Programmable I/os: 4
• Number Of Timers: 2
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOT-23-6
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

6.3
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the
Down Mode (Sleep)”
6.4
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
EXAMPLE 6-1:
 2011 Microchip Technology Inc.
MOVWF
SWAPF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
Interrupts During Sleep
INT Pin
W_TEMP
STATUS,W
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
for more details.
SAVING STATUS AND W REGISTERS IN RAM
Section 7.0 “Power-
;Copy W to TEMP register
;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
;Save status to bank zero STATUS_TEMP register
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
Preliminary
6.5
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
Note:
PIC10(L)F320/322
Context Saving During Interrupts
These devices do not require saving the
PCLATH. However, if computed GOTOs
are used in both the ISR and the main
code, the PCLATH must be saved and
restored in the ISR.
holding
Figure
Example 6-1
2-2). These 16 locations are
registers
can be used to:
DS41585A-page 45
W_TEMP
and