ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 126

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Error Reporting and Handling
and BMC will also keep track of which timer expired (early FRB2, late FRB2, or OS Watchdog)
and display the appropriate error message to the user.
All of the user options are intended to allow a system administrator to set up a system such that
during a normal boot no gap exists during POST that is not covered by the watchdog timer.
Options are provided by the BIOS to control the policy applied to OS Watchdog timer failures.
By default, an OS Watchdog Timer failure will not cause any action. Other options provided by
the BIOS are for the system to reset or power off watchdog timer failure.
6.1.5
All the failures (FRB3, FRB2, and FRB1), including the failing processor, are recorded into the
system event log (SEL). The FRB-3 failure is recorded automatically by the mBMC while the
FRB2, and FRB1 failures are logged to the SEL by the BIOS. In the case of an FRB2 failure,
some systems will log additional information into the OEM data byte fields of the SEL entry. This
additional data indicates the last POST task that was executed before the FRB2 timer expired.
This information may be useful for failure analysis.
6.2
The chipset will detect and correct single-bit errors and will detect all double-bit memory errors.
The chipset supports 4-bit single device data correction (SDDC) when in dual channel mode.
Both single-bit and double-bit memory errors are reported to baseboard management by the
BIOS, which handles SMI events generated by the MCH.
Memory Error Handling can be enabled or disabled in system BIOS Setup.
6.2.1
The MCH supports the Sparing memory RAS mode. Use BIOS Setup to configure the memory
RAS mode.
The following table shows memory error handling with the mBMC.
Note: The BIOS does not support the Memory Data Scrubber Error.
126
Memory Error Handling
Sparing mode
Memory with RAS mode
Memory Error Handling in RAS Mode
Treatment of Failed Processors
Table 59. Memory Error Handling mBMC
When sparing occurs:
- The BIOS will not report memory RAS configuration to mBMC.
- The BIOS will light the faulty DIMM LED.
DIMMs that go offline during operating system runtime will be
back online on the next system reboot without user intervention.
Sparing states are not sticky across system reset.
Intel order number C91056-002
Server Board SE7320VP2
Intel® Server Board SE7320VP2
Revision 2.1