ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 46

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Functional Architecture
3.4.3
The integrated IDE controller of the 6300ESB ICH provides two IDE channels. These IDE
channels are capable of supporting up to two drives for each channel. A standard 40-pin IDE
connector on the baseboard interfaces with the primary IDE channel signals. The signals of the
secondary IDE channel are routed to the high-density 100-pin front panel/floppy/IDE connector
for use in either the Intel
SR2400 (2U chassis). The IDE channels can be configured and enabled or disabled by
accessing the BIOS Setup Utility during POST.
The BIOS supports the ATA/ATAPI Specification, version 6 or later. It initializes the embedded
IDE controller in the chipset south-bridge and the IDE devices that are connected to these
devices. The BIOS scans the IDE devices and programs the controller and the devices with
their optimum timings. The IDE disk read/write services that are provided by the BIOS use PIO
mode, but the BIOS will program the necessary Ultra DMA registers in the IDE controller so that
the operating system can use the Ultra DMA modes.
The BIOS initializes and supports ATAPI devices such as LS-120/240, CDROM, CD-RW and
DVD.
The BIOS initializes and supports S-ATA devices just like P-ATA devices. It initializes the
embedded the IDE controllers in the chipset and any S-ATA devices that are connected to these
controllers. From a software standpoint, S-ATA controllers present the same register interface
as the P-ATA controllers. Hot plugging S-ATA drives during the boot process is not supported
by the BIOS and may result in undefined behavior
3.4.3.1
The IDE interfaces of the 6300ESB ICH DMA protocol redefines signals on the IDE cable to
allow both host and target throttling of data and transfer rates of up to 100MB/s.
3.4.3.2
The BIOS supports the ATA/ATAPI Specification, version 6 or later. The BIOS initializes the
embedded IDE controller in the chipset (6300ESB ICH) and the IDE devices that are connected
to these devices. The BIOS scans the IDE devices and programs the controller and the devices
with their optimum timings. The IDE disk read/write services that are provided by the BIOS use
PIO mode, but the BIOS programs the necessary Ultra DMA registers in the IDE controller so
that the operating system can use the Ultra DMA Modes.
3.4.4
The integrated Serial ATA (SATA) controller of the 6300ESB provides two SATA ports on the
baseboard. The SATA ports can be enabled/disabled and/or configured by accessing the BIOS
Setup Utility during POST.
The SATA function in the 6300ESB has dual modes of operation to support different operating
system conditions. In the case of native IDE-enabled operating systems, the 6300ESB has
separate PCI functions for serial and parallel ATA. To support legacy operating systems, there
is only one PCI function for both the serial and parallel ATA ports. The MAP register provides
the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through
the SATA registers. A software write to the Function Disable Register (D31, F0, offset F2h, bit 1)
46
IDE Support
Ultra ATA/100
IDE Initialization
SATA Support
®
Server Chassis SR1400 LC (1U chassis) or the Intel
Intel order number C91056-002
Intel® Server Board SE7320VP2
®
Server Chassis
Revision 2.1