ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 29

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
Each function within the 6300ESB ICH has its own set of configuration registers. Once
configured, each appears to the system as a distinct hardware controller sharing the same PCI
bus interface.
3.2.2.1
The 6300ESB ICH PCI interface provides a 33MHz, Revision 2.3 compliant implementation. All
PCI signals are 5V tolerant, except for PME#. The 6300ESB ICH integrates a PCI arbiter that
supports up to four external PCI bus masters in addition to the internal 6300ESB ICH requests.
On the Server Board SE7320VP2 this PCI interface supports two on-board PCI devices: the
ATI* video controller and the Intel
3.2.2.2
The fast IDE interface supports up to four IDE devices, providing an interface for IDE hard disks
and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports
PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec. It does not
consume ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal
transfers. The 6300ESB ICH’s IDE system contains two independent IDE signal channels. They
can be electrically isolated independently. They can be configured to the standard primary and
secondary channels (four devices).
3.2.2.3
The SATA controller supports two SATA devices, providing an interface for SATA hard disks
and ATAPI devices. The SATA interface supports PIO IDE transfers up to 16 Mb/s and Serial
ATA transfers up to 1.5 Gb/s (150 MB/s). The 6300ESB ICH’s SATA system contains two
independent SATA signal ports. They can be electrically isolated independently. Each SATA
device can have independent timings. They can be configured to the standard primary and
secondary channels. The Server Board SE7320VP supports two SATA connectors for internal
hard disks supporting RAID levels 0 and 1.
3.2.2.4
The 6300ESB ICH implements an LPC Interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The Low Pin Count (LPC) bridge function of the 6300ESB ICH
resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0
contains other functional units including DMA, interrupt controllers, timers, power management,
system management, GPIO, and RTC.
3.2.2.5
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.
The 6300ESB ICH supports two types of DMA: LPC and PC/PCI. LPC DMA and PC/PCI DMA
use the 6300ESB ICH’s DMA controller. The PC/PCI protocol allows PCI-based peripherals to
initiate DMA cycles by encoding requests and grants via two PC/PC REQ#/GNT# pairs. LPC
Revision 2.1
PCI Interface
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
SATA Controller
Low Pin Count (LPC) Interface
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
Intel order number C91056-002
®
82541PI Network Interface Controller.
Functional Architecture
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