ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 30

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ADWPCIXRSKU20

Manufacturer Part Number
ADWPCIXRSKU20
Description
Manufacturer
Intel
Datasheet

Specifications of ADWPCIXRSKU20

Lead Free Status / Rohs Status
Supplier Unconfirmed
Functional Architecture
DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on
LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the
LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4
is reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The 6300ESB ICH provides an ISA-compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 82C59 interrupt controllers. The two interrupt controllers are
cascaded so 14 external and two internal interrupts are possible. In addition, the 6300ESB ICH
supports a serial interrupt scheme. All of the registers in these modules can be read and
restored. This is required to save and restore the system state after power has been removed
and restored to the platform.
3.2.2.6
In addition to the standard ISA-compatible PIC described in the previous section, the 6300ESB
ICH incorporates the Advanced Programmable Interrupt Controller (APIC).
3.2.2.7
The 6300ESB ICH contains an Enhanced Host Controller Interface (EHCI) specification for
Universal Serial Bus, Revision 1.0-compliant host controller that supports USB high-speed
signaling. The high-speed USB 2.0 allows data transfers up to 480 Mb/s, which is 40 times
faster than full-speed USB.
The 6300ESB ICH also contains four Universal Host Controller Interface (UHCI) controllers that
support USB full-speed and low-speed signaling. On the Server Board SE7320VP2, the
6300ESB ICH supports four USB 2.0 ports. All four ports are high-speed, full-speed, and low-
speed capable. 6300ESB ICH’s port-routing logic determines whether a USB port is controlled
by one of the UHCI controllers or by the EHCI controller.
3.2.2.8
The 6300ESB ICH contains a Motorola* MC146818A-compatible real-time clock with 256 bytes
of battery backed RAM. The real-time clock performs two key functions: keeping track of the
time of day and storing system data, even when the system is powered down. The RTC
operates on a 32.768 KHz crystal and a separate 3V lithium battery.
The RTC supports two lockable memory ranges. By setting bits in the configuration space, two
8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of
passwords or other system security information.
The RTC supports a date alarm that allows for scheduling a wake up event up to 30 days in
advance. The RTC is designed and verified to meet the following accuracy: +/- 2 seconds/day
for the non-condensing environmental range of temperatures from 10-35ºC.
30
Advanced Programmable Interrupt Controller (APIC)
Universal Serial Bus (USB) Controller
RTC
Intel order number C91056-002
Intel® Server Board SE7320VP2
Revision 2.1