ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 31

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
3.2.2.9
General-purpose inputs and outputs are provided for custom system design. The number of
inputs and outputs varies depending on the 6300ESB ICH configuration. All unused GPI pins
must be pulled high or low, so that they are at a predefined level and do not cause undue side
effects.
3.2.2.10
The 6300ESB ICH’s power management functions include enhanced clock control, local and
global monitoring support for 14 individual devices, and various low-power (suspend) states,
such as Suspend-to-DRAM and Suspend-to-Disk. A hardware-based thermal management
circuit permits software-independent entrance to low-power states. The 6300ESB ICH contains
full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision
2.0b.
3.2.2.11
The 6300ESB ICH contains an SMBus host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I
are implemented. The 6300ESB ICH’s SMBus host controller provides a mechanism for the
processor to initiate communications with SMBus peripherals (slaves).
The 6300ESB ICH supports slave functionality, including the Host Notify protocol. Hence, the
host controller supports eight command protocols of the SMBus interface: Quick Command,
Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write,
and Host Notify. See the System Management Bus (SMBus) Specification, Version 2.0 for more
information.
3.3
The MCH provides an integrated memory controller for direct connection to two channels of
registered DDR-266, DDR-333 or DDR2-400 memory (stacked or unstacked). Peak theoretical
memory data bandwidth using DDR-266 technology is 4.26 GB/s and 5.33 GB/S for DDR-333
technology. For DDR2-400 technology, this increases to 6.4 GB/s.
The MCH supports a burst length of four, whether in single or dual channel mode. In dual
channel mode this results in eight 64-bit chunks (64-byte cache line) from a single read or write.
In single channel mode, two reads or writes are required to access a cache line of data.
3.3.1
The memory controller is capable of supporting up to four loads per channel for DDR-333, and
DDR2-400. Memory technologies are classified as being either single rank or dual rank
depending on the number of DRAM devices that are used on any one DIMM. A single rank
DIMM is a single load device. Single rank = one load. Dual rank DIMMs are dual load device.
Dual rank = two loads.
Revision 2.1
Memory Sub-System
Memory Sizing
General Purpose I/O (GPIO)
Enhanced Power Management
System Management Bus (SMBus 2.0)
Intel order number C91056-002
2
C devices. Special I
Functional Architecture
2
C commands
31