ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 173

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ADWPCIXRSKU20

Manufacturer Part Number
ADWPCIXRSKU20
Description
Manufacturer
Intel
Datasheet

Specifications of ADWPCIXRSKU20

Lead Free Status / Rohs Status
Supplier Unconfirmed
Intel® Server Board SE7320VP2
8.2.6
The output voltages shall remain within limits specified for the step loading and capacitive
loading specified in the table below. The load transient repetition rate shall be tested between
50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only
a test specification. The ∆ step load may occur anywhere within the MIN load to the MAX load
conditions.
Notes
8.2.7
The power supply shall be stable and meet all requirements with the following capacitive
loading ranges.
8.2.8
The power supply shall be unconditionally stable under all line/load/transient load conditions
including capacitive load ranges. A minimum of: 45 degrees phase margin and -10dB-gain
margin is required. Closed-loop stability must be ensured at the maximum and minimum loads
as applicable.
8.2.9
The Common Mode noise on any output shall not exceed 350mV pk-pk over the frequency
band of 10Hz to 30MHz.
Revision 2.1
1.
2.
3.
+3.3V
+5V
12V1+12V2+12V3
+5VSB
Step loads on each 12V output may happen simultaneously.
For Load Range 2 (light system loading), the tested step load size should be 60% of those listed.
The +12V should be tested with 1000µF evenly split between the three +12V rails.
Output
Dynamic Loading
Capacitive Loading
Closed Loop Stability
Common Mode Noise
+3.3V
+5V
+12V(1, 2, 3)
-12V
+5VSB
Output
5.0A
4.0A
20.0A
0.5A
Table 110. Capacitve Loading Conditions
Table 109. Transient Load Requirements
∆ Step Load Size
(See note 2)
Intel order number C91056-002
250
400
500 each
1
20
MIN
0.25 A/µsec
0.25 A/µsec
0.25 A/µsec
0.25 A/µsec
Load Slew Rate
6,800
4,700
11,000
350
350
Design and Environmental Specifications
MAX
µF
µF
µF
µF
µF
250 µF
400 µF
2200 µF
20 µF
Units
Test Capacitive Load
1, 3
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