ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 36

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Functional Architecture
The extended memory test is configured using the BIOS Setup Utility. The coverage of the test
can be configured to one of the following:
The “interleave width” of a memory subsystem is dependent on the chipset configuration. By
default, both the base and extended memory tests are configured to the Disabled setting. The
extended memory test can be aborted by pressing the <Space> key during the test.
3.3.5
Both the baseboard management controller and the BIOS provide support for memory failure
LEDs, and failure/state transition events. The following table shows which memory monitoring
features are supported on the Server Board SE7320VP2.
DIMM failure can be detected at BIOS POST or during system operation. POST detected DIMM
failures or mis-configuration (incompatible DIMM sizes/speeds/etc) cause the BIOS to disable
the failed/affected DIMMs and generate IPMI SEL events, which are sent to the BMC in use.
The BIOS is responsible for DIMM FRU LED management and illuminates the LEDs associated
with failed or disabled DIMMs.
3.3.6
The Intel E7320 MCH supports several memory RASUM (Reliability, Availability, Serviceability,
Usability, and Manageability) features. These features include the Intel
Correction (Intel
Retry on Correctable Errors, Integrated Memory Initialization, and DIMM Sparing. The following
sections describe how each is supported.
Note: The operation of the memory RASUM features listed below are supported on the Server
Board SE7320VP2. However, the system has limited memory monitoring and logging
capabilities. It is possible for a RASUM feature to be initiated without notification that the action
has occurred.
3.3.6.1
The DRAM interface uses two different ECC algorithms. The first is a standard SEC/DED ECC
across a 64-bit data quantity. The second ECC method is a distributed, 144-bit S4EC-D4ED
36
Test every location (Extensive)
Test one interleave width per kilo-byte of memory (Sparse)
Test one interleave width per mega-byte of memory (Quick)
Memory Monitoring
Memory RASUM Features
DRAM ECC – Intel
®
x4 SDDC) for memory error detection and correction, Memory Scrubbing,
Inventory
Correctable Error Reporting
Uncorrectable Error Reporting
Table 7. Memory Monitoring Support
Memory Feature
Intel order number C91056-002
®
x4 Single Device Data Correction (Intel
Supported
Yes
No
No
Intel® Server Board SE7320VP2
®
x4 Single Device Data
®
x4 SDDC)
Revision 2.1