ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 128

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Error Reporting and Handling
disabled. Such an entry indicates a serious hardware problem that must be repaired at the
earliest possible time.
The system BIOS implements this feature for two types of errors, correctable memory errors
and correctable bus errors. If ten errors occur in a single wall-clock hour, the corresponding
error handler disables further reporting of that type of error. A unique counter is used for each
type of error; i.e., an overrun of memory errors does not affect bus error reporting.
The BIOS re-enables logging and SMIs the next time the system is rebooted.
6.3
This section defines how errors are handled by the system BIOS. Also discussed is the role of
the BIOS in error handling and the interaction between the BIOS, platform hardware, and server
management firmware with regard to error handling. In addition, error-logging techniques are
described and beep codes for errors are defined.
One of the major requirements of server management is to correctly and consistently handle
system errors. System error sources can be categorized as follows:
Sensors are managed by the mBMC. The mBMC is capable of receiving event messages from
individual sensors and logging system events
6.3.1
The SMI handler handles and logs system-level events that are not visible to the server
management firmware. If SEL error logging is disabled in the BIOS Setup utility, no SMI signals
are generated on system errors. If error logging is enabled, the SMI handler preprocesses all
system errors, even those that are normally considered to generate an NMI.
The SMI handler sends a command to the mBMC to log the event and provides the data to be
logged. For example, The BIOS programs the hardware to generate an SMI on a single-bit
memory error and logs the location of the failed DIMM in the system event log.
6.3.1.1
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. The BIOS can be instructed to enable or disable reporting the
PERR# and SERR# through NMI. Disabling NMI for PERR# and/or SERR# also disables
logging of the corresponding event. In the case of PERR#, the PCI bus master has the option to
retry the offending transaction, or to report it using SERR#. All other PCI-related errors are
reported by SERR#. All the PCI-to-PCI bridges are configured so that they generate a SERR#
128
Error Logging
PCI bus
Memory multi-bit errors (single-bit errors are not logged)
Sensors
Processor internal errors, bus/address errors, thermal trip errors, temperatures and
voltages, and GTL voltage levels
Errors detected during POST, logged as POST errors
SMI Handler
PCI Bus Error
Intel order number C91056-002
Intel® Server Board SE7320VP2
Revision 2.1