ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 33

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
The BIOS reads the Serial Presence Detect (SPD) SEEPROMs on each installed memory
module to determine the size and timing of the installed memory modules. The memory-sizing
algorithm determines the size of each bank of DIMMs. The BIOS programs the memory
controller in the chipset accordingly. The total amount of configured memory can be found using
BIOS Setup.
3.3.2
Mixing of DDR-266 and DDR-333 DIMMs is supported between banks of memory. However,
when mixing DIMM types, DDR-333 will run at DDR-266 speeds.
Using the following algorithm, BIOS configures the memory controller of the MCH to run in
either dual channel mode or single channel mode:
Revision 2.1
1. If one or more fully populated DIMM banks are detected, set the memory controller to
2. If DIMM 1A is present, set the memory controller to single channel mode A. Otherwise,
3. If Channel 1B DIMM is present, set the memory controller to single channel mode B.
dual channel mode. Otherwise, go to step 2.
go to step 3.
Otherwise, generate a memory configuration error.
Memory Population
MCH
Figure 5. Identifying Banks of Memory
Intel order number C91056-002
3A
Bank 3
3B
2A
Bank 2
2B
1A
Bank 1
1B
Functional Architecture
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