ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 61

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel® Server Board SE7320VP2
3.5.1.4
The chipset supports System Management Mode (SMM) operation in one of three modes.
System Management RAM (SMRAM) provides code and data storage space for the SMI_L
handler code, and is made visible to the processor only on entry to SMM, or other conditions
that can be configured using Intel E7320 chipset.
The MCH supports three SMM options:
Three abbreviations are used later in the table that describes SMM Space Transaction
Handling.
Notes:
Revision 2.1
Compatible SMRAM (C_SMRAM)
High Segment (HSEG)
Top of Memory Segment (TSEG)
High SMM is different than in previous chipsets. In previous chipsets the high segment
was the 384KB region from A_0000h to F_FFFFh. However, C_0000h to F_FFFFh was
not useful so it is deleted in MCH.
TSEG SMM is different than in previous chipsets. In previous chipsets, the TSEG
address space was offset by 256MB to allow for simpler decoding and the TSEG was
remapped to directly under the TOLM. In the MCH, the TSEG region is not offset by
256MB and it is not remapped.
0
1
1
1
1
Global Enable
Compatible (C)
High (H)
TSEG (T)
G_SMRAME
System Management Mode Handling
SMM Space
Enabled
X
0
0
1
1
High Enable
H_SMRAME
A0000h to BFFFFh
0FEDA0000h TO 0FEDBFFFFh
(TOLM-TSEG_SZ) to TOLM
Intel order number C91056-002
Transaction Address Space
Table 18. SMM Space Table
X
0
1
0
1
TSEG Enable
TSEG_EN
(Adr)
Disable
Enable
Enable
Disable
Disable
Compatible
(C) Range
A0000h to BFFFFh
A0000h to BFFFFh
(TOLM-TSEG_SZ) to
TOLM
DRAM Space (DRAM)
Disable
Disable
Disable
Enable
Enable
High (H)
Range
Functional Architecture
Disable
Disable
Enable
Disable
Enable
TSEG (T)
Range
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