ADWPCIXRSKU20 Intel, ADWPCIXRSKU20 Datasheet - Page 65

• Manufacturer Part Number: ADWPCIXRSKU20
• Manufacturer: Intel

Specifications of ADWPCIXRSKU20

• Lead Free Status / Rohs Status: Supplier Unconfirmed

31
Intel® Server Board SE7320VP2
3.5.3.1
CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure.
Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the
selected bus. Bits [10:8] choose a specific function in a multi-function device. Bit [8::2] select a
specific register in the configuration space of the selected device or function on the bus.
3.6
All buses on the baseboard operate using synchronous clocks. Clock synthesizer/driver circuitry
on the baseboard generates clock frequencies and voltage levels as required, including the
following:
The PCI-X slot speed on the full-length riser card is determined by the riser card in use.
Revision 2.1
30
Reserved
Enable bit (‘1’ = enabled, ‘0’ = disabled)
Clock Generation and Distribution
200MHz differential clock at 0.7V logic levels. For Processor 0, Processor 1, Debug Port
and MCH
100MHz differential clock at 0.7V logic levels on CK409B. For DB800 clock buffer
100MHz differential clock at 0.7 Vlogic levels on DB800. For PCI Express Device is
MCH, which includes x4 PCI Express Slot. For SATA is 6300ESB ICH
66MHz at 3.3V logic levels: For E7320 and 6300ESB ICH
48MHz at 3.3V logic levels: For 6300ESB ICH and SIO
33MHz at 3.3V logic levels: For 6300ESB ICH, Video, mBMC and SIO
14.318MHz at 2.5V logic levels: For 6300ESB ICH and video
10Mhz at 5V logic levels: For mBMC
CONFIG_ADDRESS Register
24
23
Bus Number
Figure 11. CONFIG_ADDRES Register
Intel order number C91056-002
16
15
Device
11
10
Function
8
Functional Architecture
7
Register
1
0
65
0
0