CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 61

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

Bits 7–4: UNUSED. Read = 0000b, Write = don’t care.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Bits 7–2: UNUSED. Read = 000000b, Write = don’t care.
Bit 1:
Bit 0:
R/W
R/W
Bit7
Bit7
—
—
RXINH: Receive Inhibit
Setting this bit to ‘1’ temporarily inhibits new packet reception. If a packet is currently being
received, reception will continue until the packet is received. Once set, this bit must be cleared to ‘0’
by software to resume packet reception.
RXCLRV: Valid Bit Clear
Writing a ‘1’ to this bit clears the valid bit of the current packet, freeing up the buffer for new packets.
This action should only be started after all bytes of the current packet have been read (CPEND = 1).
If the packet is not completely read, RXSKIP should be used to discard the remaining bytes.
RXSKIP: Skip Current Packet
Writing a ‘1’ to this bit updates discards the current packet by clearing its valid bit and advances the
AutoRead buffer pointer to the beginning of the next packet.
RXCLEAR: Receive Buffer Clear
Writing a ‘1’ to this bit discards all packets in the receive buffer and resets all buffer pointers and
valid bits to zero. Note: Any packets currently in the buffer will remain in memory, however, all infor-
mation such as the starting address and length of each packet will be lost. Any new packets that
arrive will overwrite the existing data.
CPEND: Current Packet End Reached
This bit is automatically cleared by hardware when the valid bit for the current packet is cleared (see
RXCLRV description) or the current packet is discarded (see RXSKIP description).
0: The last byte of the current packet has not been read using the AutoRead interface.
1: The last byte of the current packet has been read using the AutoRead interface.
RXBUSY: Receiving Packet
0: Receive interface is idle.
1: Receive interface is currently receiving a packet.
R/W
R/W
Bit6
Bit6
—
—
Register 34. RXCN: Receive Interface Control
Register 35. RXSTA: Receive Interface Status
R/W
R/W
Bit5
Bit5
—
—
R/W
R/W
Bit4
Bit4
—
—
RXINH
R/W
R/W
Bit3
Bit3
—
Rev. 1.0
RXCLRV
R/W
Bit2
Bit2
—
W
RXSKIP RXCLEAR 00000000
CPEND
Bit1
Bit1
W
R
RXBUSY 00000000
Bit0
Bit0
W
R
CP2200/1
Reset Value
Reset Value
Address:
Address:
0x12
0x11
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