CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 81

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

Bit 15:
Bit 14:
Bits 13–5:Reserved. Read = varies; Must write 000000000b.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Reserved RANDRST
Bit15
R/W
R/W
Bit7
Reserved. Read = varies; Must write 0b.
RANDRST: Random Number Generator Reset
Writing a ‘1’ to this bit resets the random number generator within the transmit function.
LOOPBCK: Loopback Mode Enable Bit
Note: MAC Loopback Mode is independent of the physical layer loopback mode.
0: Normal operation.
1: MAC transmit data is internally looped back as MAC receive data.
TXPAUSE: TX Flow Control Enable Bit (Full-Duplex Only)
0: PAUSE control frames are blocked.
1: PAUSE control frames are allowed to pass through the MAC.
RXPAUSE: RX Flow Control Enable Bit (Full-Duplex Only)
0: PAUSE control frames received from the physical layer are ignored.
1: PAUSE control frames received from the physical layer are acted upon.
Reserved. Read = 0; Must write 0b.
RCVEN: Receive Enable
0: The MAC blocks control frames from reaching the receive interface. The MAC blocks all received
1: The MAC allows received packets to reach the receive interface.
Reserved
packets from the receive interface.
Bit14
R/W
R/W
Bit6
Indirect Register 1. MACCN: MAC Control Register
Bit13
R/W
R/W
Bit5
LOOPBCK TXPAUSE RXPAUSE Reserved
Bit12
R/W
R/W
Bit4
Bit11
R/W
R/W
Bit3
Rev. 1.0
Reserved
Bit10
R/W
R/W
Bit2
R/W
Bit9
R/W
Bit1
RCVEN
R/W
Bit8
R/W
Bit0
CP2200/1
Default Value
MACADDR:
0x8000
0x00
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