ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 12

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ISP1761ET

Manufacturer Part Number
ISP1761ET
Description
USB Interface IC USB 2.0 HS OTG HOST
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1761ET

Operating Supply Voltage
1.65 V to 3.6 V
Lead Free Status / Rohs Status
 Details
Other names
ISP1761ET,557

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NXP Semiconductors
Table 2.
ISP1761_4
Product data sheet
Symbol
CS_N
RD_N
WR_N
GNDD
BAT_ON_N
DC_IRQ
HC_IRQ
DC_DREQ
HC_DREQ
V
HC_DACK
DC_DACK
REG1V8
HC_SUSPEND
/WAKEUP_N
DC_SUSPEND
/WAKEUP_N
GNDC
CC(I/O)
[1][2]
Pin description
Pin
LQFP128
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
…continued
Ball
TFBGA128
A12
B12
B11
A11
C10
A10
B10
A9
B9
C8
A8
B8
B7
A7
C6
A6
Type
I
I
I
-
OD
O
O
O
O
P
I
I
P
I/OD
I/OD
-
[3]
Rev. 04 — 5 March 2007
Description
chip select assertion indicates the ISP1761 being accessed; active
LOW
input, 3.3 V tolerant
read enable; active LOW
input, 3.3 V tolerant
write enable; active LOW
input, 3.3 V tolerant
digital ground
to indicate the presence of a minimum 3.3 V on pins 6 and 7
(open-drain); connect to V
output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant
Peripheral Controller interrupt signal
output 4 mA drive, 3.3 V tolerant
Host Controller interrupt signal
output 4 mA drive, 3.3 V tolerant
DMA controller request for the Peripheral Controller
output 4 mA drive, 3.3 V tolerant
DMA controller request for Host Controller
output 4 mA drive, 3.3 V tolerant
digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling
capacitor; see
Host Controller DMA request acknowledgment; when not in use,
connect to V
input, 3.3 V tolerant
Peripheral Controller DMA request acknowledgment; when not in
use, connect to V
input, 3.3 V tolerant
core power output (1.8 V); internal 1.8 V for the digital core; used for
decoupling; connect a 100 nF capacitor; for details on additional
capacitor placement, see
Host Controller suspend and wake-up; 3-state suspend output
(active LOW) and wake-up input circuits are connected together
connect to V
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
Peripheral Controller suspend and wake-up; 3-state suspend output
(active LOW) and wake-up input circuits are connected together
connect to V
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
core ground
HIGH = output is 3-state; the ISP1761 is in suspend mode
LOW = output is LOW; the ISP1761 is not in suspend mode
HIGH = output is 3-state; the ISP1761 is in suspend mode
LOW = output is LOW; the ISP1761 is not in suspend mode
CC(I/O)
CC(I/O)
CC(I/O)
Section 7.7
CC(I/O)
through a 10 k pull-up resistor
through an external 10 k pull-up resistor
through an external 10 k pull-up resistor
through a 10 k pull-up resistor
Section 7.7
CC(I/O)
through a 10 k pull-up resistor
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
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