R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1032
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R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
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Section 17 I
17.3.2
ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I
Page 1002 of 1448
Bit
7
6
5
4
3
2
Bit Name
BBSY
SCP
SDAO
⎯
SCLO
⎯
I
2
C Bus Interface 2 (IIC2)
2
C Bus Control Register B (ICCRB)
0
1
1
1
1
1
Initial Value
R/W
R/W
R/W
R
R/W
R
⎯
Description
Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start and stop
conditions in master mode. This bit is set to 1
when the SDA level changes from high to low
under the condition of SCL = high, assuming that
the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low
to high under the condition of SCL = high,
assuming that the stop condition has been issued.
Write 1 to BBSY and 0 to SCP to issue a start
condition. Follow this procedure when also re-
transmitting a start condition. Write 0 to BBSY and
0 to SCP to issue a stop condition. To issue a
start/stop condition, use the MOV instruction.
Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop
conditions in master mode.
To issue a start condition, write 1 in BBSY and 0
in SCP. A retransmit start condition is issued in
the same way. To issue a stop condition, write 0 in
BBSY and 0 in SCP. This bit is always read as 1.
If 1 is written, the data is not stored.
This bit monitors SDA output level. When reading
and SDA0 is 1, the SDA pin outputs high. When
reading and SDA0 is 0, the SDA pin outputs low.
The write value should always be 1.
Reserved
The write value should always be 1.
This bit monitors SCL output level. When reading
and SCLO is 1, the SCL pin outputs high. When
reading and SCLO is 0, the SCL pin outputs low.
Reserved
This bit is always read as 1.
2
C control.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
2
C bus is
Jul 22, 2010
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