R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 425

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
Figures 8.20 and 8.21 show an example of the setting procedure for block transfer mode in
common register enabled mode and common register disabled mode, respectively.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Figure 8.20 Example of Block Transfer Mode Setting Procedure
and transfer destination
Set number of transfers
Block transfer mode
Set transfer source
Read DMABCRL
Set MDLCFGCR
Set DMABCRH
Set DMABCRL
Block transfer
Set DMACRF
mode setting
Set DRSEL
addresses
(Common Register Enabled Mode)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Set the DMCOMMD bit in MDLCFGCR to 1.
[2] Set RSEL4 or RSEL5 bit in DRSEL to 1 depending on the
[3] Set each bit in DMABCRH.
[4] Set the transfer source address in SAR and transfer
[5] Set the block size in both ETCRAH and ETCRAL.
[6] Set each bit in DMACRF.
[7] Read DTE = 0 and DTME = 0 in DMABCRL.
[8] Set each bit in DMABCRL.
channel to be set.
destination address in DAR.
Set the number of transfers in ETCRB.
•
•
• Specify enabling or disabling of internal interrupt
• Set the transfer data size with the DTSZ bit.
• Specify whether SAR is to be incremented,
• Set the BLKE bit to 1 to select block transfer mode.
• Specify whether the transfer source or the transfer
• Specify whether DAR is to be incremented,
• Select the activation source with bits DTF3 to DTF0.
clearing with the DTA bit.
decremented, or fixed, with the SAID and SAIDE bits.
destination is a block area with the BLKDIR bit.
decremented, or fixed, with the DAID and DAIDE bits.
to the CPU with DTIE bit.
transfer.
Specify enabling or disabling of transfer end interrupts
Set both the DTME and DTE bits to 1 to enable
Section 8 DMA Controller (DMAC)
Page 395 of 1448