R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 116

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Section 3 MCU Operating Modes
3.2
The following registers are related to the operating mode setting.
3.2.1
MDCR monitors the current operating mode of this LSI.
Note:
3.2.2
SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash
memory control registers, sets the external bus mode, and enables or disables on-chip RAM.
Page 86 of 1448
Bit
7 to 3
2
1
0
Bit
7, 6
5
Mode control register (MDCR)
System control register (SYSCR)
Bit Name
MACS
*
Register Descriptions
Mode Control Register (MDCR)
System Control Register (SYSCR)
Bit Name
MDS2
MDS1
MDS0
Determined by the settings of pins MD2 to MD0.
Initial Value
All 1
0
Initial Value
All 0
⎯*
⎯*
⎯*
R/W
R/W
R/W
R/W
R
R
R
Descriptions
Reserved
The initial value should not be modified.
MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction performs non-saturation operation
1: MAC instruction performs saturation operation
Descriptions
Reserved
These bits are always read as 0 and cannot be
modified.
Mode Select 2 to 0
These bits indicate the input levels at mode pins
MD2 to MD0 (the current operating mode). Bits
MDS2 to MDS0 correspond to pins MD2 to MD0,
respectively. These bits are read-only bits and so
they cannot be modified. The input levels of the
MD2 to MD0 pins are latched into these bits when
MDCR is read. These latches are canceled by a
reset.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010

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