R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 747

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Notes: 1. Not supported in the H8S/2427 Group.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
3
2
1
0
2. Not supported in the 5-V version.
Bit Name
PH3DDR
PH2DDR
PH1DDR
PH0DDR
Initial Value
0
0
0
0
R/W
W
W
W
W
Description
•
Pin PH1 functions as the SDRAMφ*
when the SDPSTP bit is 0 in the H8S/2427R
Group. In the H8S/2427 Group or when the
SDPSTP bit is 1 in the H8S/2427R Group, if bit
CS5E is set to 1 while area 5 is specified as
normal space, pin PH1 functions as the CS5
output pin when bit PH1DDR is set to 1, and
functions as an I/O port when the bit is cleared to
0. When bit CS5E is cleared to 0, pin PH1 is an
I/O port, and its function can be switched with bit
PH1DDR. When area 5 is specified as DRAM
space*
functions as the RAS5*
port when the bit is cleared to 0.
Pin PH0 functions as the CS4 output pin when bit
PH0DDR is set to 1 while area 4 is specified as
normal space and bit CS4E is set to 1. If bit
PH0DDR is cleared to 0, pin PH0 functions as an
I/O port. When bit CS4E is cleared to 0, pin PH0
is an I/O port, and its function can be switched
with bit PH0DDR. When area 4 is specified as
DRAM space*
functions as the RAS4*
port when the bit is cleared to 0. When areas 2 to
5 are specified as continuous SDRAM space*
pin PH0 functions as the WE output pin when bit
CS4E is set to 1, and as an I/O port when the bit
is cleared to 0.
Modes 3, 5, and 7 (when EXPE = 0)
Pins PH3, PH2, and PH0 are I/O ports, and their
functions can be switched with PHDDR.
Pin PH1 functions as the SDRAMφ*
when the SDPSTP bit is 0 in the H8S/2427R
Group. In the H8S/2427 Group or when the
SDPSTP bit is 1 in the H8S/2427R Group, pin
PH1 is an I/O port and its function can be
switched with PHDDR.
2
and bit CS5E is set to 1, pin PH1
2
and bit CS4E is set to 1, pin PH0
2
2
output pin and as an I/O
output pin and as an I/O
Section 11 I/O Ports
1
1
output pin
output pin
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