R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 245

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
7.6.5
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR,
WTCRAH, RDNCR, and CSACR.
(1)
Figure 7.21 shows the bus timing for an 8-bit, 2-state data access space. When an 8-bit access
space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used.
Wait states cannot be inserted in the data cycle.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
8-Bit, 2-State Data Access Space
Read
Write
Basic Timing
Notes: 1. n = 6, 7
AD15 to AD8
AD15 to AD8
Address bus
Figure 7.21 Bus Timing for 8-Bit, 2-State Data Access Space
2. When RDNn = 0
HWR
LWR
CSn
RD
AH
φ
Tma1
Address cycle
Address
Address
Tma2
T1
Data cycle
Write data
Section 7 Bus Controller (BSC)
T2
Read
data
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