R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 417

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.5.6
In common register enabled mode, normal mode can be selected by setting the RSEL4 and RSEL5
bits in DRSEL corresponding to channels 4 and 5 to 1 and clearing the BLKE bit in DMACRF to
0. In common register disabled mode, normal mode can be specified by clearing the BLKE bit in
DMACRF to 0. In normal mode, SAR and DAR are updated after data transfer of a byte or word
in response to a single transfer request, and this is executed the number of times specified in
ETCRA. The transfer source is specified by SAR, and the transfer destination by DAR. Table 8.8
summarizes register functions in normal mode.
Table 8.8
SAR and DAR specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. SAR and DAR can be incremented or decremented by 1 or 2 each time a
byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value
can be set separately for SAR and DAR.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time
a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCR in common
register enabled mode or the DTE bit in DMAECRF in common register disabled mode is cleared
and transfer ends. If the DTIE bit in DMABCR in common register enabled mode or the DTIE bit
in DMAECRF in common register disabled mode is set to 1 at this time, an interrupt request is
sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is
65,536.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Register
23
23
15
Normal Mode
ETCRA
Register Functions in Normal Mode
SAR
DAR
0
0
0
Source address
register
Destination
address register
Transfer counter Number of transfers Decremented every
Function
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Section 8 DMA Controller (DMAC)
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
transfer; transfer ends
when count reaches
H'0000
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