R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 514

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 9 EXDMA Controller (EXDMAC)
(3)
In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a
transfer request is accepted. The next transfer request is accepted after the end of a one-transfer-
unit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated
before the next EXDMA cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 9.35 to 9.38 show operation timing examples for various conditions.
Page 484 of 1448
φ pin
EDREQ
EDRAK
Bus cycle
ETEND
EDA bit
External Request/Cycle Steal Mode/Normal Transfer Mode
Figure 9.35 External Request/Cycle Steal Mode/Normal Transfer Mode
1
Bus release
(No Contention/Dual Address Mode/Low Level Sensing)
EXDMA
read
EXDMA
write
Bus release
3 cycles
Last transfer cycle
EXDMA
read
H8S/2427, H8S/2427R, H8S/2425 Group
EXDMA
write
REJ09B0565-0100 Rev. 1.00
0
Bus release
Jul 22, 2010