R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 951

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
5
4
3
Bit Name
ORER
ERS
PER
Initial Value
0
0
0
R/W
R/(W) * Overrun Error
R/(W) * Error Signal Status
R/(W) * Parity Error
Description
Indicates that an overrun error occurred while
receiving and the reception has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
[Setting condition]
•
[Clearing conditions]
•
Indicates that a parity error occurred while receiving
in asynchronous mode and the reception has ended
abnormally.
[Setting condition]
•
[Clearing condition]
•
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1.
When 0 is written to ORER after reading ORER
= 1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
When the low level of the error signal is
sampled
When 0 is written to ERS after reading ERS = 1
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1.
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
Page 921 of 1448