R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 335

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
(a)
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 7.91 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
DQMU, DQML
Precharge-sel
Figure 7.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Address bus
Data bus
Normal space access after a continuous synchronous DRAM space read access
CKE
CAS
RAS
WE
RD
φ
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
PALL ACTV READ
address 1
Column
T
p
Continuous synchronous
DRAM space read
address
address
Row
Row
T
r
Column address 1
T
c1
T
cl
High
T
c2
Idle cycle
T
i
External space read
External address
External address
T
1
NOP
T
2
T
3
Section 7 Bus Controller (BSC)
Continuous synchronous
DRAM space read
T
i
Column address 2
READ
T
c1
Page 305 of 1448
T
Cl
NOP
T
c2