R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 258

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
7.7.2
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
7.6 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
Table 7.6
[Legend]
×:
7.7.3
If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 7.5.1, Data
Size and Data Alignment.
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Row
address
Column
address
MXC2 MXC1 MXC0
Don't care.
0
1
0
1
Address Multiplexing
Data Bus
DRAMCR
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
0
1
×
×
×
0
1
0
1
×
×
×
Shift
Size
10 bits
11 bits
8 bits
9 bits
⎯
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A15 A14 A13 A12 A11 A10 A9
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
A15 A14 A13 A12 A11 A10
Reserved (setting prohibited)
Reserved (setting prohibited)
Address Pins
A9
A8
A8
H8S/2427, H8S/2427R, H8S/2425 Group
A7
A7
A6
A6
REJ09B0565-0100 Rev. 1.00
A5
A5
A4
A4
A3
A3
A2
A2
Jul 22, 2010
A1
A9
A1
A0
A8
A9
A0