R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 334

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
(b) Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space
write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to
be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit
in DRACCR. Figure 7.90 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
(8)
Note: The synchronous DRAM interface is not supported by the H8S/2427 Group and H8S/2425
Page 304 of 1448
Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM
Space Access:
UCAS, LCAS
Address bus
Group.
HWR, LWR
Data bus
Figure 7.90 Example of Idle Cycle Operation after DRAM Write Access
RAS
RD
φ
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
T
p
DRAM space read
T
r
T
c1
T
c2
Idle cycle
T
i
External space read
T
1
T
2
H8S/2427, H8S/2427R, H8S/2425 Group
T
3
DRAM space read
REJ09B0565-0100 Rev. 1.00
T
c1
T
c2
Jul 22, 2010