R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 431

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
(4)
Figure 8.26 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is
generated during data transfer, block transfer operation is not affected until data transfer for one
block has ended.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Address bus
Full Address Mode (Block Transfer Mode)
TEND
Figure 8.26 Example of Full Address Mode Transfer (Block Transfer Mode)
Bus release
HWR
LWR
RD
φ
DMA
read
DMA
write
Block transfer
DMA
read
DMA
write
DMA
dead
Bus release
DMA
read
DMA
write
Last block transfer
DMA
read
Section 8 DMA Controller (DMAC)
DMA
write
DMA
dead
Page 401 of 1448
Bus
release