R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 324

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
(3)
If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the read cycle.
Figure 7.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Page 294 of 1448
Read after Write
Address bus
CS (area A)
CS (area B)
HWR, LWR
Data bus
Figure 7.79 Example of Idle Cycle Operation (Read after Write)
RD
φ
(a) No idle cycle insertion
T
(ICIS2 = 0)
1
Bus cycle A
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS2 = 1, initial value)
T
H8S/2427, H8S/2427R, H8S/2425 Group
2
T
3
REJ09B0565-0100 Rev. 1.00
Idle cycle
T
i
Bus cycle B
T
1
T
2
Jul 22, 2010