CD2231 Intel Corporation, CD2231 Datasheet - Page 10



Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Intel Corporation
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
DMA Controller Features
Other Features
Enhanced features for UNIX environment
Programmable timer closely coupled with character reception, especially for asynchronous
receive DMA operation
Automatic baud rate detection — single carriage return
DMA or interrupt selectable per channel and per direction
Dual Configuration register sets to reduce realtime constraints
Append and Block mode DMA
Chain/unchain of long frames into multiple buffers
32-bit address and 8- or 16-bit data transfer
Programmable gap in buffers following a receive character exception
Improved interrupt schemes
Easily cascadable for multiple-device configurations
16-byte receive and transmit FIFOs
Local and Remote Maintenance Loopback modes
Two independent bit-rate generators per channel for transmit and receive
On-chip NRZ (nonreturn-to-zero), NRZI (nonreturn-to-zero inverted), and Manchester data
encoding and decoding
DPLL (digital phase locked loop) on each receiver
Two independent timers per channel
Byte-endian-orientation selection pin allows easy interface to 80X86 and 680X0 processors
Eight clock/modem control signals per channel (in addition to TxD and RxD) on CD2231
Compatible with the CD24XX family of communication controllers
— Character expansion in transmit (for example, sending <LF> will be expanded to <CR>
— Programmable translation of receiving character with error to different pattern (for
— Flow-control transparency and LNext
— Vectored interrupts per channel allow direct jump into proper service routines
— Good Data interrupts eliminate need for status checks
<LF> automatically)
example, character with parity error can be translated into FFh, 00h, character on the
system side)

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