CD2231 Intel Corporation, CD2231 Datasheet - Page 62
CD2231
Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
1.CD2231.pdf
(178 pages)
- Current page: 62 of 178
- Download datasheet (3Mb)
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
62
Table 8.
Bit Rate Constants, CLK = 35 MHz (Sheet 2 of 2)
Transmit and receive data can be encoded and decoded in NRZ, NRZI, or Manchester formats. For
NRZI, at the start of transmission, a learning datastream of contiguous zeros achieves bit
synchronization; for Manchester, an alternating pattern of ones and zeros is required.
NRZ, NRZI, and Manchester are data encoding schemes used in various synchronous protocols. In
NRZ, the signal condition represents the data type, high for a logic ‘1’ and low for a logic ‘0’. In
NRZ and NRZI encoding, the transitions of the datastream occur at the beginning of the bit cell. In
NRZI encoding, the signal condition switches to the opposite state to send a binary ‘0’. In
Manchester encoding, the transitions are always in the middle of the bit cell. A high-to-low
transition is made to send a logic ‘1’, and a low-to-high transition to send a logic ‘0’. The timing
diagrams
Example 3
This example illustrates programming the DPLL at 128 kbits/second in NRZI mode, using the
internal clock at a system clock frequency of 33 MHz.
Divisor loaded into RCOR = 38 or 26h
Value loaded into RCOR = 28h, to enable the DPLL, NRZI framing and select Clk 0
Example 4
This example illustrates programming the DPLL in the 1 External Clock mode, with Manchester
encoding.
Divisor loaded into RBPR = 01h, to enable 1 external clock
Value loaded into RCOR = 36h, to enable the DPLL, select Manchester framing, and external
clock
When using an n-times external clock, the highest possible clock frequency and largest divisor
combination is recommended. The frequency of an external clock should be less than the system
CLK input divided by 16, (that is, for 33-MHz operation, the data clock should be less than 2.0
MHz). Note that R(T)BPR is an 8-bit register, therefore the largest divisor value is 255.
Bit Rate
4800
7200
9600
19200
38400
56000
64000
76800
115200
12800
134400
NOTE: All divisors are in hexadecimal.
(Figure 11
to
Figure
Divisor
13) illustrate the encoding method. The data bits are ‘0110010’.
e3
97
71
e3
71
4d
43
38
25
21
20
Clock
Clk 1
Clk 1
Clk 1
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
0.06%
0.06%
0.06%
0.06%
0.06%
0.16%
0.53%
0.06%
0.06%
0.53%
1.38%
Error
Datasheet
Related parts for CD2231
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CD-ROM, DVD Multimedia IC
Manufacturer:
China Hua Jing Electronics Group Co.
Part Number:
Description:
Cd-rom
Manufacturer:
ROHM Electronics
Datasheet:
Part Number:
Description:
CD-ROM spindle motor driver
Manufacturer:
Rohm
Datasheet:
Part Number:
Description:
CD Digital Signal Processor
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
CD Digital Servo Signal Processor
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
CD Digital Signal Processor
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
CD Servo Controller
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
Cd Electronic Shockproof Controller
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
Cd Servo Controller With Mcu With Interface Supporting Sc9831 Wma/mp3 Encoding/decoding
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
Cd Digital Servo Signal Processor Slave Mode
Manufacturer:
Silan
Datasheet:
Part Number:
Description:
Cd Digital Servo Signal Processor With Mcu 2/4 Digits Lcd Display And Remote Control
Manufacturer:
Silan
Datasheet: