CD2231 Intel Corporation, CD2231 Datasheet - Page 144
Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Register Name: BRBSTS
Register Description: Receive Buffer ‘B’ Status
Default Value: x’00
Access: Byte Read/Write
Register Name: RCBADRL
Register Description: Current Receive Buffer Address, lower word
Default Value: x’0000
Access: Word Read Only
B Receive Buffer Status (BRBSTS)
These registers contain the current status of associated receive buffers and enable the buffers to be
passed between the host and CD2231.
When the Buffer Complete bit is set by the CD2231, the buffer is free for the host to process.
(RBCNT information is updated to the number of bytes available in the buffer, and a new buffer
can be allocated.)
Receive Current Buffer Address Register — Lower (RCBADRL)
Bus error (set by the CD2231 and cleared by the host CPU)
0 = No bus error
1 = Bus error occurred on the last transfer; the suspect address is available in
End of frame (set by the CD2231 and cleared by the host CPU)
0 = This buffer does not terminate a frame.
1 = This buffer terminates a frame.
Buffer complete (set by the CD2231 and cleared by the host CPU)
0 = Buffer not complete.
1 = Buffer complete.
Reserved – must be ‘0’.
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2231)
0 = Buffer not free to be used by CD2231.
1 = Buffer free to be used by CD2231.
Binary address value, 32-bit address, bits 15:8
Binary address value, 32-bit address, bits 7:0
Motorola Hex Address: x’4E
Motorola Hex Address: x’3E
Intel Hex Address: x’4D
Intel Hex Address: x’3C