CD2231 Intel Corporation, CD2231 Datasheet - Page 134

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.5.3.2
134
Register Name: TIR
Register Description: Transmit Interrupt
Default Value: None, value varies
Access: Byte Read only
Bit 7
Ten
Transmit Interrupt Register (TIR)
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:2
Bit 1
Bit 0
Bit 6
Tact
Ten
Transmit enable is set by the CD2231 to initiate a transmit interrupt request
sequence. It is cleared during a valid transmit interrupt acknowledge cycle.
Tact
Transmit active is set automatically when Ten is set, and the Fair Share logic allows
the assertion of a transmit interrupt request. It is cleared when the host CPU writes
to the Transmit End of Interrupt register.
Teoi
Transmit end of interrupt is set automatically when the host CPU writes to the Trans-
mit End of Interrupt register while in a transmit interrupt routine.
Reserved – always returns ‘0’ when read.
Tvct [1:0]
Transmit Vector bits are set by the CD2231 to provide the lower two bits of the vec-
tor supplied to the host CPU during an interrupt acknowledge cycle. Transmit vector
is decoded as follows: Tvct [1] = 1, and Tvct [0] = 0.
Reserved – always returns ‘0’ when read.
Tcn [0]
Transmit channel number is set by the CD2231 to indicate the channel requiring
transmit interrupt service.
Bit 5
Teoi
Ten
0
1
1
0
0
Tact
Bit 4
0
0
1
1
0
0
Teoi
0
0
0
0
1
Tvct [1]
Bit 3
Sequence of Events
Idle
Transmit interrupt requested, but not asserted
Transmit interrupt asserted
Transmit interrupt acknowledged
Transmit interrupt service routine completed
Tvct [0]
Bit 2
Motorola Hex Address: x’EC
Bit 1
Intel Hex Address: x’EE
0
Datasheet
Tcn [0]
Bit 0