CD2231 Intel Corporation, CD2231 Datasheet - Page 43

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

5.4.1
5.4.2
Datasheet
The CD2231 can perform DMA operations in any of the supported line protocols. A special
Append mode feature can reduce host CPU overhead for asynchronous datastreams. DMA
operations are channel- and direction-specific. In each channel, either the transmitter and the
receiver, or both, can be independently programmed for DMA mode by the CMR (Channel Mode
register).
When the CD2231 acquires the bus for a DMA transfer, only data for one channel and in one
direction is transferred; then, bus ownership is relinquished. A maximum of 16 bytes — the depth
of the transmit and receive FIFOs — are transferred during any ownership cycle.
Whenever possible, DMA cycles are 16 bits wide, and buffers have the proper byte alignment.
Unaligned buffers are sent using only 8-bit-wide transfers. If the buffer begins on an even address
and contains an odd number of bytes, the CD2231 uses 16-bit transfers for all the words in the
buffer except the last transfer, which is 8 bits.
If one buffer in a chain ends on an odd address, the next buffer in the chain should also start on an
odd address to maintain proper alignment for most efficient bus usage. In this case, only the last
transfer of the first buffer and the first transfer of the next buffer is 8 bits wide; all others are 16
bits.
The CD2231 can be forced to perform only byte-wide DMA operations by setting the byteDMA
(DMR[3]) bit in the DMR (DMA Mode register).
Bus Acquisition Cycle
In
DMA Data Transfer
After the CD2231 acquires the bus, it pulses ADLD* once. This loads the upper 24 address bits to
the external 24-bit latch. This happens only once per DMA grant cycle. The AD[0–15] bits are
remapped to memory address (MA) bits MA[16–31] and A[0–7] are mapped to MA[8–15]. If
during DMA the upper 24 bits need to change, the CD2231 relinquishes the bus and then re-
acquires the bus.
During each DMA read and write cycle, the least-significant eight memory address bits, MA[0–7],
come from A[0–7].
In
1. CD2231 asserts BR* and waits for BGIN*.
2. When BGIN* is detected, the CD2231 can access the bus after the current bus owner
3. If BGACK* is high when BGIN* goes low, then the bus is free to access. Go to step 5.
4. If BGACK* is low when BGIN* goes low, then the bus is in use. The CD2231 waits for
5. Once the CD2231 senses that BGACK* is high, the CD2231 waits for the current bus cycle to
Figure
Figure
relinquishes control of the bus.
BGACK* to go high.
terminate (DS* and DTACK* high) and then assert BGACK* by driving it low. At that time,
the CD2231 owns the bus. After driving BGACK* low, the CD2231 drives BR* high.
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
5, the CD2231 was required to wait to access the bus.
6, one DMA access is shown after the bus is acquired.
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