CD2231 Intel Corporation, CD2231 Datasheet - Page 152

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.6.5.14
8.6.5.15
8.7
8.7.1
152
Register Name: TCBADRL
Register Description: Current Transmit Buffer Address, lower word
Default Value: x’0000
Access: Word Read Only
Register Name: TCBADRU
Register Description: Current Transmit Buffer Address, upper word
Default Value: x’0000
Access: Word Read Only
Register Name: TPR
Register Description: Timer Period
Default Value: x’FF
Access: Byte Read/Write
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Transmit Current Buffer Address Register — Lower (TCBADRL)
Transmit Current Buffer Address Register — Upper (TCBADRU)
These registers contain the address of the current DMA buffer being used for transmit data; this
address is updated at the end of transmit data transfers. In the case of a bus error during transmit
data transfer, this register contains the start address of the transfer causing the bus error.
Timer Registers
Timer Period Register (TPR)
Bit 14
Bit 14
Bit 6
Bit 6
Bit 6
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
Binary address value, 32-bit address, bits 31:24
Binary address value, 32-bit address, bits 23:16
Binary address value, 32-bit address, bits 15:8
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
Binary value
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
Bit 10
Bit 10
Bit 2
Bit 2
Bit 2
Motorola Hex Address: x’3A
Motorola Hex Address: x’DA
Motorola Hex Address: x’38
Bit 9
Bit 1
Bit 9
Bit 1
Bit 1
Intel Hex Address: x’38
Intel Hex Address: x’3A
Intel Hex Address: x’D8
Datasheet
Bit 8
Bit 0
Bit 8
Bit 0
Bit 0

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