CD2231 Intel Corporation, CD2231 Datasheet - Page 86



Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Intel Corporation
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
HDLC DMA Channel Setup Example
This per-channel initialization code example is for the HDLC protocol at 64 kbps (with CLK = 33
MHz) with NRZI encoding. The setup specifies two extra opening flags before frames, no address
matching, and that DMA transfers should be used.
Receive DMA Interrupt Service Routine
The following code example shows an interrupt service routine for the CD2231 in DMA mode.
The buffer class array ib[ ] is used for notational convenience, and its exact implementation is user-
defined. The upper ( ) and lower ( ) functions should return the upper and lower 16 bits of the
DMA address for the current buffer segment. The ‘nxt_buf()’ accesses the next segment.
If the system uses separate interrupt handlers for receive, transmit, and modem interrupts, the
channel number can be obtained from the least-significant bit of the Interrupt register (RIR, TIR,
MIR). Otherwise, first use the LIVR to determine the type of interrupt. Receive Good Data
interrupts should not occur during DMA transfers. The normal exception is when end-of-frame is
The DMABSTS register shows which buffer the CD2231 expects to use next. Fill the descriptor
registers for that buffer, including the 2231own bit and return. The last access to the CD2231
during the service routine is the REOIR.
int risrl = inportb( RISRL ); // low status
int ch = inportb( RIR ) & 0x01;// channel number
switch( inport(LIVR) & 0x03 ) {
outportb( CMR, ASYNC );// Async Mode, interrupt
outportb( COR1, PARIGN | CHAR8 );// 8 bit chars, no parity
outportb( COR2, IXM | TXIBE );// in-band flow,implied XON
outportb( COR3, STOP1 | FCT );// 1 stop, flow control
outportb( COR4, thresh );// FIFO threshold
outportb( COR5, 0 );
outportb( LIVR, 0x30 );// Set interrupt vector
outportb( RCOR, DPLL_NRZI );// Receive clock option
outportb( RBPR, x’3F );// Baud rate divisor
outportb( TCOR, 0 );
outportb( TBPR, x’3F );// Baud rate divisor
outportb( CMR, RX_DMA | TX_DMA | HDLC );// Mode register
outportb( CPSR, CPSR_CRC_V41 );// CRC polynomial select
outportb( COR1, NO_ADDR | FLAG_2 );// No address matching,
outportb( COR2, CRC_V41 );// 2 opening flags
outportb( COR3, 0 );
outportb( COR4, thresh );// FIFO threshold
outportb( COR5, 0);
if( risrl & RISR_EOF ) {
if( inportb(DMABSTS) & DMABS_NRBUF ) {// buffer B next
outport( BRBADRU, ib[ch].upper() );
// Transmit clock option
// shouldn’t happen in DMA
// EOF is ’normal’ exception

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